The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component or line that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down also produces a relatively high power dissipation value, which may be addressed by using low power dissipation devices such as complementary metal-oxide-semiconductor (CMOS) devices. CMOS devices have typically been formed with a gate oxide and polysilicon gate electrode. There has been a desire to replace the gate oxide and polysilicon gate electrode with a high-k gate dielectric and metal gate electrode to improve device performance as feature sizes continue to decrease. In other schemes of metal integration, some form of damascene processing may be involved in which patterns are etched into a dielectric and then the patterns are filled with metal layers by blanket deposition onto the wafer surface, for example by chemical vapor deposition (CVD).
Chemical mechanical polishing (CMP) has become a key technology driver to achieve local or global wafer planarization for submicron advanced semiconductor ICs. The CMP process is used to planarize and remove excess metal over the dielectric and to produce a planar semiconductor structure wherein the metal lines or plugs, barrier metal, and exposed dielectric surfaces are coplanar.
A cleaning process is required after the CMP process to remove contamination introduced during polishing, such as from metal contaminants, slurry, and other particles. However, the cleaning process should not corrode the metal lines or cause defects in the metal line topography. In the past, isopropyl alcohol (IPA) has been used as a final cleaning step to dry processed wafers. However, after vaporization of the IPA, the wafer surfaces have been kept in an open atmosphere environment potentially causing metal corrosion, metal line topography defects (e.g., pitting) from oxidation and moisture in the atmosphere, and/or time dependent dielectric breakdown.
Accordingly, improved post-metal CMP cleaning methods and apparatus for performing such methods are highly desired.